15/04/2024 | Parttime | Cambridge | CV-LibraryAn understanding of ASIC/SoC prototyping, which features can and cannot be implemented in FPGA. Excellent written and spoken English; ability to write coherent documentation. “Nice To Have” Skills and Experience Strong RTL skills in either (System) Verilog or VHDL. Knowledge and expertise in debugging
Save for laterRegister your CV15/04/2024 | Parttime | Cambridge | CV-LibraryFor complex ASIC products & SoCs using Verilog and/or SystemVerilog Experience with Arm-based designs and/or Arm System Architectures Knowledge or experience with Functional Safety concepts and standards (e.g., ISO 26262, IEC 61508). Should have worked on an Automotive IP or SoC from definition to completion
Save for laterRegister your CV15/04/2024 | Parttime | Sheffield | CV-LibraryDesign, specifically within server & data centre SoC environments. You will also need strong experience with hardware simulation, validation tools, and IO compliance testing. Proficient in high-speed digital design, hardware description languages (Verilog/VHDL), and digital logic design. In-depth
Save for laterRegister your CV15/04/2024 | Parttime | Cambridge | CV-LibraryDesign, specifically within server & data centre SoC environments. You will also need strong experience with hardware simulation, validation tools, and IO compliance testing. Proficient in high-speed digital design, hardware description languages (Verilog/VHDL), and digital logic design. In-depth
Save for laterRegister your CV15/04/2024 | Parttime | Cambridge | CV-LibraryTo develop comprehensive verification strategies Creating and reviewing design verification documentation Designing and implementing SystemVerilog/UVM based verification IP and testbenches Improving existing testbenches to increase performance, quality and efficiency Testing and debugging Verilog RTL
Save for laterRegister your CV15/04/2024 | Parttime | Cambridge | CV-LibraryWill also guide and support other members of the team. Required Skills and Experience Experience of RTL design for complex SoC development using Verilog and/or SystemVerilog Experience or knowledge in the following areas Static design checks, Synthesis and timing analysis, Power management techniques
Save for laterRegister your CV15/04/2024 | Parttime | Cambridge | CV-LibraryDesign for complex SoC development using Verilog and/or SystemVerilog Experience or knowledge in the following areas Static design checks, Synthesis and timing analysis, Power management techniques, Power and Clock domain crossing An understanding of the fundamentals of computer architecture and systems
Save for laterRegister your CV15/04/2024 | Parttime | Cambridge | CV-LibraryDescription and verification languages e.g. SystemVerilog, Verilog, VHDL. A detailed understanding and experience of the current verification strategies required for complex SoC development, including software-based techniques Good knowledge of test plan creation and tracking Bare-metal - Low-level
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