29/04/2024 | Parttime | Sheffield | CV-LibraryOf the concepts related to Synthesis, Place & Route, Clock tree synthesis, constraint development, timing closure and knowledge of hardware languages Verilog/System verilog Working experience with tools like Fusion Compiler/Genus & Innovus, Primetime/Tempus and other relevant tools required for physical
Save for laterRegister your CV29/04/2024 | Parttime | Sheffield | CV-LibraryDesign, specifically within server & data centre SoC environments. You will also need strong experience with hardware simulation, validation tools, and IO compliance testing. Proficient in high-speed digital design, hardware description languages (Verilog/VHDL), and digital logic design. In-depth
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