21/06/2024 | Parttime | Cambridge | CV-LibraryRequired Skills and Experience Experience in FPGA flows with Xilinx, including compilation, debug, performance and implementation of advanced features. Proven track record of project debug and execution individually. Deep understanding of digital design concepts and Verilog coding. Proficiency in problem
Save for laterRegister your CV17/06/2024 | Parttime | Sheffield | CV-LibraryPower, high performance sophisticated micro-architecture and RTL design using System Verilog, Verilog or VHDL in reasonable timescales. Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices. Knowledgeable on ASIC (or FPGA) design methodology, IP signoff
Save for laterRegister your CV17/06/2024 | Parttime | Cambridge | CV-LibraryDesign, specifically within server & data centre SoC environments. You will also need strong experience with hardware simulation, validation tools, and IO compliance testing. Proficient in high-speed digital design, hardware description languages (Verilog/VHDL), and digital logic design. In-depth
Save for laterRegister your CV17/06/2024 | Parttime | Cambridge | CV-LibraryPower, high performance sophisticated micro-architecture and RTL design using System Verilog, Verilog or VHDL in reasonable timescales. Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices. Knowledgeable on ASIC (or FPGA) design methodology, IP signoff
Save for laterRegister your CV17/06/2024 | Parttime | Manchester | CV-LibraryPower, high performance sophisticated micro-architecture and RTL design using System Verilog, Verilog or VHDL in reasonable timescales. Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices. Knowledgeable on ASIC (or FPGA) design methodology, IP signoff
Save for laterRegister your CV17/06/2024 | Parttime | Cambridge | CV-LibraryTo develop comprehensive verification strategies Creating and reviewing design verification documentation Designing and implementing SystemVerilog/UVM based verification IP and testbenches Improving existing testbenches to increase performance, quality and efficiency Testing and debugging Verilog RTL
Save for laterRegister your CV17/06/2024 | Parttime | Cambridge | CV-LibraryIn Verilog - System Verilog or VHDL. Excellent communications skills, written and spoken English; ability to write coherent documentation. “Nice To Have” Skills and Experience Knowledge and expertise in debugging sophisticated designs, embedded software, simulation and hardware. A creative and structured
Save for laterRegister your CV17/06/2024 | Parttime | Bristol | CV-LibraryPower, high performance sophisticated micro-architecture and RTL design using System Verilog, Verilog or VHDL in reasonable timescales. Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices. Knowledgeable on ASIC (or FPGA) design methodology, IP signoff
Save for laterRegister your CV17/06/2024 | Parttime | Sheffield | CV-LibraryDesign, specifically within server & data centre SoC environments. You will also need strong experience with hardware simulation, validation tools, and IO compliance testing. Proficient in high-speed digital design, hardware description languages (Verilog/VHDL), and digital logic design. In-depth
Save for laterRegister your CV17/06/2024 | Parttime | Cambridge | CV-LibraryDescription and verification languages e.g. SystemVerilog, Verilog, VHDL. A detailed understanding and experience of the current verification strategies required for complex SoC development, including software-based techniques Good knowledge of test plan creation and tracking Bare-metal - Low-level
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