27/05/2024 | Parttime | Bristol | CV-LibraryPower, high performance sophisticated micro-architecture and RTL design using System Verilog, Verilog or VHDL in reasonable timescales. Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices. Knowledgeable on ASIC (or FPGA) design methodology, IP signoff
Save for laterRegister your CV14/05/2024 | Fulltime | Bristol | CV-Library | £50 - £55 / Hour A week in Bristol. In order to suit the project requirement you must have experience in either of the following - At least 5 years of experience in Verilog and/or System Verilog. - Experience on IP/block level Test-bench bring up on SV UVM based platform - At least 5 years of experience in of IP
Save for laterRegister your CV10/05/2024 | Fulltime | Bristol | CV-LibraryAnd design implementations (VHDL, Simulink etc), targeting Xilinx, Intel, Microsemi devices. Verifying complex FPGA implementations using VHDL and System Verilog\UVM test-bench methodologies. Using FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Generating low-level software (C
Save for laterRegister your CV07/05/2024 | Fulltime | Bristol | CV-Library | £30,000 - £40,000 / Year Calibration Qualifications & Experience - Experience in some form of FPGA design required - Exposure to RTL design and coding experience with VHDL (or Verilog) - Knowledge of CPU or DSP architectures advantageous - Ability to learn how to develop large Altera and Xilinx FPGAs using VHDL (or Verilog
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