03/06/2024 | Parttime | Cambridge | CV-LibraryIn developing technology that makes people's lives better! Responsibilities For this role we are looking for engineers who are capable of leading the verification of a unit within a project through all phases of the design and verification flow. This includes Working closely with the RTL design team
Save for laterRegister your CV03/06/2024 | Parttime | Cambridge | CV-LibraryTo understand implementation challenges and opportunities, working with the architects to improve and refine the ideas Plan, track and coordinate tasks for yourself and your team Work with modelling, verification, performance analysis and back-end implementation colleagues to ensure your design meets all
Save for laterRegister your CV03/06/2024 | Parttime | Cambridge | CV-LibraryThat works well in a complete system. Required Skills and Experience You can demonstrate experience in working with constrained-random verification including ownership of a suitably complex verification environment. You have experience of using SystemVerilog and UVM Proven software engineering skills
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