03/04/2024 | Fulltime | Farnborough | CV-Library | £60,000 - £80,000 / Year Level Insertion of DFT test structures and chip level integration, capture, and simulation Skills needed to succeed COT/ASIC physical design flow covering Synthesis, Floor planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure
Save for laterRegister your CV03/04/2024 | Fulltime | Hampshire | CV-LibraryOf electronic and electrical sub-assemblies. - Program a range of devices including FPGA, ASIC, PIC during goods in and assembly test. - Inspection and test on internally built electrical, electronic and RF sub-assembly through to final assembly inspections. This verifying that defined process is consistently
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